Delta-sigma modulators are particularly useful in digital-to-analog and analog-to-digital converters (DACs and ADCs). Using oversampling, a delta-sigma modulator spreads the quantization noise power across an oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, the delta-sigma modulator performs noise shaping by acting as a low-pass filter to the input signal and a high-pass filter to the noise; hence, most of the quantization noise power is thereby shifted out of the signal band.
The typical delta-sigma modulator includes a summer summing the input signal with negative feedback, a linear filter, a quantizer, and a feedback loop with a digital-to-analog converter coupling the quantizer output and the inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in a higher order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer. Higher-order modulators have improved quantization noise transfer characteristics over those of lower order, but stability becomes a more critical design factor as the order increases.
Switched-capacitor based filters/integrators are useful in a number of applications including the integrator stages in delta-sigma modulators and in other data converters. Generally, a basic differential switched-capacitor integrator samples the input signal, and often a reference voltage as well, onto a corresponding pair of sampling capacitors during the sampling (charging) phase, in a process sometimes referred to as “double sampling.” During the following second phase, the charge on the sampling capacitor is transferred at the summing nodes of an operational amplifier to a corresponding pair of integrator capacitors in the amplifier feedback loops. The operational amplifier drives the integrator output. An example input network 100 for a delta-sigma modulator is depicted in FIG. 1.
Example input network 100 of FIG. 1 generally operates in accordance with a clock signal CLK, the complement of which is a signal CLK′. Each of clock signals CLK and CLK′ may comprise a square-wave signal, as shown in FIG. 1. Clock signals CLK and CLK′ may define clock cycles operating at a sampling rate wherein each clock cycle includes a first phase when clock signal CLK is high and clock signal CLK′ is low and a second phase when clock signal CLK is low and clock signal CLK′ is high. Generally, during the first phase of each cycle, switches 102 and 108 close and charges proportional to the reference voltages v+ and v− generated by reference buffers 101 at the inputs to input network 100 are respectively sampled onto cross-coupled sampling capacitors 110a and 110b, respectively. During the second phase of each cycle, switches 104 and 106 close, and the input voltages v+ and v− are coupled to the input plates of sampling capacitors 110a and 110b, respectively. Consequently the charges sampled onto sampling capacitors 110a and 110b during the first phase are respectively forced onto integration capacitors 114a and 114b which are each coupled between inputs and outputs of an integrator 112.
One disadvantage of such an input network is that kickbacks or voltage steps may occur when a sampling capacitor 110 is switched from positive reference voltage v+ to negative reference voltage v−, and vice versa. Accordingly, in such input networks (and in other data converter architectures relying on switched capacitors for sampling and other functions) buffers 100 generating reference voltages v+ and v− must be designed with adequate bandwidth to settle the kickback within a sampling window.